In recent years, development of miniaturization technique to achieve miniaturization and high densification is required along with high integration and high functionality of a semiconductor integrated circuit device. Particularly, importance of a planarization technique by chemical mechanical polishing (hereinafter referred to as CMP) has been increasing.
For example, along with miniaturization and multilayered structures of wiring of a semiconductor integrated circuit device, unevenness on the surface of each layer in production steps tends to be significant. In order to prevent such problems that the unevenness exceeds the depth of focus of photolithography, whereby no sufficient resolution will be obtained, CMP is an essential technique.
CMP is employed, specifically, for planarization of an interlevel dielectric (ILD) film, shallow trench isolation (STI), tungsten plug formation, formation of multilayered wiring comprising copper and a low dielectric film, etc. Further, it starts being applied to planarization of a premetal dielectric (PMD) film to be carried out prior to formation of metal wiring, for which a reflow process by heat treatment has been employed.
For an insulating film of e.g. ILD, STI and PMD, a silicon dioxide type is used in many cases. Heretofore, in production of a semiconductor device, for planarization of such a silicon dioxide type insulating film, silica abrasive particles have been commonly used as abrasive particles to be used for a CMP polishing compound.
On the surface of a film to be an object to be polished (hereinafter sometimes referred to as a film to be polished) in a semiconductor integrated circuit device, an uneven pattern is formed by the influence of unevenness of e.g. wiring beneath the film when it is laminated. When silica abrasive particles are applied to polishing of a silicon dioxide type film having such an uneven pattern, a sufficiently high polishing rate is obtained. However, there is a technical problem such that high level planarization is hardly realized by the following characteristics. That is, according to the degree of the pattern density of the surface unevenness (proportion of protruded pattern portions to the sum of the protruded pattern portions and recessed portions; for example, in the case of a stripe protruded pattern, the proportion of pattern widths to the sum of the pattern widths and pattern distances) and the protruded pattern size, the pattern dependence of the polishing rate at protruded portions is significant, and further, polishing is likely to proceed at a portion with a low density of protrusions and at a large size recessed portion (e.g. a portion over a wide portion between wirings). The polishing rate being influenced by the pattern density and the pattern size of the surface unevenness is called pattern dependence of the polishing rate.
Further, for planarization of a silicon dioxide type film by silica abrasive particles, the polishing amount required for planarization is large, and accordingly a film to be polished has to be formed with a large thickness in many cases, thus increasing the film formation cost and decreasing the throughput in production of a semiconductor integrated circuit device. For example, in PMD process, borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), etc. with low hardness are used, and the polishing rate of such films are very high as compared with other materials. Therefore, such a film is preliminarily formed with a large thickness and then polished to realize planarization.
The above is exemplarily described with reference to FIG. 3. FIG. 3(a) is a partial cross-section illustrating a semiconductor integrated circuit device comprising a silicon substrate 1, and a silicon dioxide film 2, a polysilicon film 3 and a BPSG film 4 laminated on the substrate, which has a protruded portion 5 and a recessed portion 6 formed on the surface of the BPSG film 4 by the influence of the polysilicon film 3. This illustrates a state before polishing.
When the BPSG film face is polished in such a structure, the recessed portions of the BPSG film are also easily polished as compared with the protruded portions, and as a result, planarization of a plane is hardly realized to bring about a state shown in FIG. 3(b) in many cases. Therefore, at present, the BPSG film 4 is made large and polished so as to reduce unevenness.
As described above, a semiconductor integrated circuit device including a silicon dioxide type material layer, particularly, a semiconductor integrated circuit device including any one of a BPSG film, a BSG film and a PSG film, the polishing rates of which are commonly high as compared with another material, has a problem that planarization of a plane to be polished is hardly achieved.
In recent years, a CMP polishing compound using cerium oxide particles as abrasive particles has been studied. A cerium oxide polishing compound provides a high polishing rate by chemical reaction of cerium oxide with the SiO moiety on the surface of a plane to be polished, on the layer surface, and is expected to improve the throughput in production of a semiconductor device. A technique to improve dispersibility of the cerium oxide polishing compound and to improve flatness of a plane to be polished, by adding a surfactant, a water-soluble polymer, a water-soluble low molecular weight compound, etc. to the cerium oxide polishing compound, is now under development.
For example, Patent Document 1 proposes an organic compound having a hydrophilic group selected from a carboxyl group and a carboxylate group, as an additive suitable for planarization of an insulating film of e.g. SiO2, SiON, SiOF, borophosphosilicate glass or phosphosilicate glass.
Further, Patent Document 2 discloses a low molecular weight additive selected from cationic water-soluble organic low molecular weight compound including a primary amine, a secondary amine, a tertiary amine and a quaternary ammonium compound, and discloses that in CMP technology to planarize an ILD film and an insulating film for STI, polishing can be carried out with high efficiency at a high rate and easily in view of process control.
Further, Patent Document 3 proposes to incorporate at least two additives of a water-soluble nitrogen-containing compound and a water-soluble anionic organic compound in a polishing compound, and discloses that such a polishing compound is a CMP polishing compound suitable for polishing of e.g. an ILD film and an insulating film for STI, which can planarize a plane to be polished at a high level at a high rate without scars, which is excellent in storage stability and with which process control is easy. The water-soluble nitrogen-containing compound is a primary amine, a secondary amine, a tertiary amine, a quaternary ammonium, polyvinyl pyrrolidone, N-alkyl-2-pyrrolidone, an aliphatic lactam or an aliphatic dicarboxylic acid imide. Further, the water-soluble anionic organic compound is a compound having a free —COOM group, a phenolic —OH group, a —SO3M group, a —OSO3M group, a —PO4M2 group or a —PO3M2 group (wherein M is a hydrogen atom, NH4 or a metal atom).
However, these Patent Documents only disclose examples of polishing a silicon dioxide film, but failed to disclose a BPSG film, a BSG film and a PSG film which are difficult to planarize. The additive disclosed in Patent Document 1 is anionic and is thereby not adsorbed in a silicon dioxide film, a BPSG film, a BSG film and a PSG film which are negatively charged in water, whereby a covering layer can not sufficiently be formed. Even if it is possible to planarize a hard silicon dioxide film, the practical polishing rates of soft BPSG film, BSG film and PSG film are very high, and a semiconductor integrated circuit device having a pattern formed thereon can not be planarized. Further, the additive disclosed in Patent Document 2 is a cationic additive and is capable of forming a covering layer, but since it is a low molecular weight additive, the covering layer forming properties are insufficient, and a semiconductor integrated circuit device with a BPSG film, a BSG film and a PSG film can not be planarized either. Patent Document 3 proposes at least two additives of a water-soluble nitrogen-containing compound and a water-soluble anionic organic compound, but the water-soluble nitrogen-containing compound is substantially equal to the low molecular weight additive disclosed in Patent Document 2, and the polishing rates of a BPSG film, a BSG film and a PSG film are very high, and a semiconductor integrated circuit device can not be planarized either. Further, the pH of the CMP polishing compound is considered to be preferably from 3 to 9, more preferably from 7.0 to 9.0 in view of the stability, the selective polishing properties, workability, handling properties, etc. However, within this pH region, the polishing rates of a BPSG film, a BSG film and a PSG film can not effectively be controlled.
Patent Document 1: Japanese Patent No. 3278532
Patent Document 2: JP-A-2001-7061
Patent Document 3: JP-A-2001-185514
Patent Document 4: JP-A-11-12561
Patent Document 5: JP-A-2001-35818